Square Kilometre Array Update

Sean Dougherty and Russ Taylor

 

With colleagues in Australia, the Canadian SKA Consortium has established an Austrailan SKA Pathfinder Science Working group co-chaired by Simon Johnson and Russ Taylor.  Other Canadian members are Sean Dougherty, Ingrid Stairs and Jasper Wall. This group is a subcommittee of the Canadian SKA Science Advisory Committee (see www.ska.ca). The first task of the working group was the development of an ASKAP Science case with contributions from several scientists in Canada and Australia.  The science case focussed on key survey science that can be done with the pathfinder as a step toward phase I SKA.  A synopsis of the science case will appear in the Publication of the Astronomical Society of Australia (Johnston et al. 2007). The full science case will be published as a special issue of Experimental Astronomy in 2008. 

 

The University of Calgary Centre for Radio Astronomy is organizing a special session on the Square Kilometre Array at ANTEM/URSI, the 13th International Symposium on Antenna Technology and Applied Electromagnetics, in Banff, Alberta on July 27-30, 2008.  Further information on the symposium will soon appear at http://antem.ee.umanitoba.ca. 

 

Canadian SKA Technology Development

 

Canadian SKA-related technology development is targeting low-cost, high-performance solutions in three areas vital to the SKA: wide field-of-view, low system-temperature, and large collecting area.  These three areas are being addressed respectively by phased focal-plane array feeds (the PHAD project), reflector antennas fabricated with composite materials (the CART project), and high-performance uncooled low-noise amplifiers. In this issue, two new areas of research at the University of Calgary are reported: low-power high-speed A/D converters, and multi-dimensional filters as beam formers..

 

PHased-Array Demonstrator (PHAD)

 

End-to-end integration of the Phased-Array Feed Demonstrator (PHAD) has now been completed.  The system is shown in Fig.2 prior to installation in the anechoic chamber for spherical near-field scanner tests.  A rear-view of the array in Fig. 3 shows the receivers subsystems.  The signals from the Vivaldi elements are amplified and down converted to baseband, then combined onto twisted-pair CAT-5 ethernet and LVD SCSI cables.  The signals are delivered to an SMA patch panel and fed to a commercial digital-signal processing system, purchased from Lytrech Signal Processing in Quebec, for sampling and recording for off-line analysis and beam forming. 

 

The PHAD array has 180 elements (9x10 for each orthogonal linear polarization), spaced half-wavelength at 2 GHz, capable of operating from 1-2 GHz with a system temperature of ~70K.  There are 32 additional elements around the perimeter of the array that are terminated. The maximum sample rate is 100 Msamples/s with 12-bit resolution. There are a number of important aspects to this system. First, the signals from all the elements will be recorded for off-line beam forming. Recording the data permits experiment and direct comparison of various beam-forming techniques on the same data.  Second, the array is sufficiently large that truncation effects are minimal at the centre of the array.  Lastly, both polarizations are sampled in order to measure polarization properties, explore calibration techniques, and devise methods to mitigate instrumental effects.

 

The Vivaldi array was put through a series of tests prior to integration with receivers.  The radiation patterns of a many representative elements were measured. The key result is the patterns are well behaved and suitable for reflector illumination. The impedance match of the inner elements was also found to be acceptable.  Unlike some arrays described in the literature that had strong resonances, the PHAD array has only one weak resonance.

 

The complete PHAD has now been installed in the anechoic chamber to commence a system shakedown and initial beam forming experiments.  In the spring and summer PHAD will move outdoors onto the CART 10-m composite reflector for testing (see below).

 

In addition to the hardware, we are now beginning to address a number of outstanding issues related to the astronomical performance of phased-array feeds using simulation software developed at DRAO.

 

 

Figure 1 – PHAD comes to life! The complete 180-element dual-polarization array assembly shown during a laboratory test. The data acquisition system is seen at centre and the power response of the elements is seen on the right (the insert at upper right shows the screen output).  A polarization shifter is seen on the left that is used to show the reception shift from vertical elements (shown) to the horizontal elements as the shifter is rotated. This prototype phased array feed system will be mounted on the new CART 10-m composite antenna after testing in a near-field range.

 

 

 

Figure 2: A rear view of the PHAD array showing the receiver subsystems and the data transmission cabling.

 

Composite Reflector Antennas

 

The ability to build large collecting areas with cost-effective reflectors having excellent radio-frequency performance remains a significant technology challenge for future radio telescopes. The CART project (Composite Applications for Radio Telescopes) at DRAO is addressing this challenge by applying composite materials and fabrication techniques to low cost-per-unit-area radio-telescope applications.

 

CART achieved a major milestone in September when the first 10-m prototype reflector was removed from the mold and mounted on a positioner (Fig. 3). The reflector weighs 1 tonne and has a surface accuracy of ~1mm rms.  The weight is a small fraction of the weight of a conventional metal reflector of similar size. This high strength-to-weight ratio provides a surface that has very little change in deflection with elevation and will allow substantial reduction on the mechanical load requirements of the telescope mount.  Holography measurements were made in mid-October to confirm physical measurements made with a laser tracker. Using a receiver built from commercial parts, a correlator provided by ATNF, and the help of Mike Kesteven (ATNF), two Ku band geostationary satellites were raster scanned at a frequency of about 12 GHz. The results (Fig. 4) show that the RF reflector is consistent with the laser tracker measurements and confirm that low-cost vacuum infused composite reflector technology, developed at DRAO, can yield high performance reflectors that operate well upto 15 GHz.  This is an excellent first result and the prospect of making 30-GHz reflectors at costs comparable to 10-GHz metal appears achievable.

 

Although these results demonstrate excellent performance for the prototype reflector, they also show that improvements can be made, and the team is now busy designing and planning the Mk2 reflector to be built from the same 10-m mold in Spring 2008 at DRAO. The Mk2 program will target improvements in cure characteristics, structural design, design-for-production and mass production methods.

 

 

 

Figure 3: The CART 10-m prototype reflector (aka. Mk1) during holography tests at DRAO on 23 October 2007. The metal patch near the lower edge of the reflector was added for test.

 

Figure 4: Holography results from the 10-m prototype reflector that demonstrates excellent agreement with the physical measurements taken with a laser tracker. The prototype has a surface rms of ~1mm, and would operate well up to15 GHz. The Mk2 design and a modified manufacturing process will remove the largest deflections seen in the image.

 

CMOS Low-Noise Amplifiers

 

The availability of very-low-noise amplifiers operating at room temperature is key to producing sensitive, low-cost, phased-array receiver systems, since cryo-cooling systems for the large number of amplifiers required for such feeds would be very expensive. Although traditional HEMT technology has had little improvement over the past decade, the CMOS technology used in computer chips has been advancing at an exponential rate described by Moore's Law.  As transistors are made smaller, they not only work at higher frequencies, but they also have lower noise.

 

Although this reduction in noise has been predicted for some time, only recently has it been demonstrated.  The University of Calgary Centre for Radio Astronomy team working on high performance room-temperature low noise amplifiers has completed measurements of two CMOS LNAs designed in 90nm CMOS.  A single-ended LNA designed to interface with an 85-Ohm antenna has achieved less than 0.2dB (<14K) of noise figure at room temperature over a bandwidth of 0.8-1.4GHz (Fig. 5).  The results of this work have been published in the November issue of the IEEE Journal of Solid-State Circuits.  A differential LNA designed for 100 Ohm differential antenna impedance was measured using a novel differential noise measurement technique developed at the University of Calgary.  These measurements verified the expectation that a differential LNA and a single-ended LNA achieve similar noise figures (Fig. 6).  The measurement technique and the measurement results have been accepted for publication by the IEEE Transactions on Instrumentation and Measurement.  Currently, the researchers at Calgary are developing a new LNA design for 65nm CMOS.

 

The Calgary and HIA-DRAO teams will be working together in the near future to integrate phased array feed elements with the room temperature CMOS LNAs. 

 

 

Figure 5: Measured minimum noise for an 85 Ohm antenna using two different room-temperature CMOS LNA’s at 0.8-1.6 GHz. 0.2dB is equivalent to 14K.

Figure 6: Measured noise figure of the differential LNA at 0.5-2 GHz.

 

 

Multi-dimensional filters for beam forming.

 
The Multidimensional Digital Signal Processing Group at the University of Calgary has pioneered the synthesis, design and implementation of directional 2D and 3D digital filters. The group has shown that such filters are capable of selectively enhancing propagating broad-band plane waves, received over an array of antennas, with high fidelity up to almost half the Nyquist frequency.  Over the last several years, this work has led to high-throughput systolic VLSI architectures for 3D IIR narrow beam filters, using novel pipelining and look-ahead techniques, to synchronously process all A/D-converted antenna signals in a single clock cycle.  High-speed prototypes have been implemented in FPGA technology. The group is now exploring the application of this method to the beam-forming problem for both aperture and focal-plane arrays.

 

Low-power high-speed A/D converters

 

The Radio-Frequency Integrated Circuit (RFIC) research group at the University of Calgary Centre for Radio Astronomy is developing a new architecture for a high-speed low-power time-based analog-to-digital converter (ADC). The time-based architecture consists of two stages.  The first stage, known as a voltage-to-time converter (VTC), takes in an analog voltage signal and outputs a series of pulses.  Each pulse is delayed by an amount proportional to the input signal at that particular moment.  As a result, the signal is transferred from the voltage domain to the time domain, since the signal information is entirely contained within these delays.  The function of the second stage, the time-to-digital converter (TDC), is to measure the delay of each pulse with respect to a reference clock and produce an N-bit digital output.  The signal is thus transferred from the time-domain to the digital domain, completing the analog-to-digital conversion. This ADC architecture has been shown to produce excellent dynamic performance, low power, and high sampling rate, and has an advantage of being able to directly trade speed for resolution.

 

The first prototype time-based ADC is a 5-bit 1GS/s design in 130nm CMOS which has a measured power consumption of 2mW (Fig. 7).  The second-generation design, a 3-bit 20GS/s ADC in a 90nm CMOS process, is currently being fabricated (Fig. 8). Future plans include the development of a 4GS/s time-based ADC with increased resolution (5-8 bits). It is projected that such a 5-bit, 4 GS/s ADC will consume ~25 mW and occupy less than 2 mm2 of silicon area in the 90nm CMOS semiconductor process. The ADC power consumption using the time-based ADC architecture is projected to increase linearly with each extra bit of resolution. Process and temperature variations will be addressed by implementing an advanced digital calibration scheme.

 

Figure 7: Prototype 5 bit, 1 GSample/s 130 CMOS ADC.

 

Figure 8: Design layout of a 3 bit, 20 GSample/s 90 nm CMOS ADC